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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD1881A one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 ac?7 soundmax codec functional block diagram g a m g a m g a m sync bit_clk phat stereo g a m mv mv AD1881A mic1 mic2 aux cd video line_out_l mono_out line_in phone_in line_out_r g = gain a = attenuate m = mute mv = master volume nc = no connect oscillators xtl_out xtl_in cs1 eapd mode reset sdata_in cs0 mode/synchronizer sdata_out g a m g a m g a m 16-bit d/a converter 16-bit d/a converter pc_beep phat stereo mv lnlvl_out_r lnlvl_out_l 0db/ 20db selector pga pga 16-bit a/d converter 16-bit a/d converter sample rate generators ac link d a m g a m nc nc pop pop a m ac97 2.1 features variable sample rate true line-level output supports secondary codec modes ac97 features designed for ac97 analog i/o component 48-lead lqfp package multibit converter architecture for improved s/n ratio greater than 90 db 16-bit stereo full-duplex codec four analog line-level stereo inputs for connection from line, cd, video, and aux two analog line-level mono inputs for speakerphone and pc beep mono mic input switchable from two external sources high quality cd input with ground sense stereo line-level output mono output for speakerphone or internal speaker power management support enhanced features mobile low power mixer mode digital audio mixer mode full duplex variable 8 khz to 48 khz sampling rate with 1 hz resolution phat? stereo 3d stereo enhancement split power supplies (3.3 v digital/5 v analog) extended 6-bit master volume control audio amp power-down signal soundmax is a registered trademark and phat is a trademark of analog device, inc.
C2C rev. 0 AD1881A?pecifications analog input parameter min typ max unit input voltage (rms values assume sine wave input) line_in, aux, cd, video, phone_in, pc_beep 1 v rms 2.83 v p-p mic with +20 db gain (m20 = 1) 0.1 v rms 0.283 v p-p mic with 0 db gain (m20 = 0) 1 v rms 2.83 v p-p input impedance * 20 k ? input capacitance * 5 7.5 pf master volume parameter min typ max unit step size (0 db to ?4.5 db); line_out_l, line_out_r 1.5 db output attenuation range span * ?4.5 db step size (0 db to 46.5 db); mono_out 1.5 db output attenuation range span * ?6.5 db mute attenuation of 0 db fundamental * 80 db programmable gain amplifier?dc parameter min typ max unit step size (0 db to 22.5 db) 1.5 db pga gain range span 22.5 db analog mixer?nput gain/amplifiers/attenuators parameter min typ max unit signal-to-noise ratio (snr) cd to line_out 90 db other to line_out 90 db step size (+12 db to ?4.5 db): (all steps tested) mic, line_in, aux, cd, video, phone_in, dac 1.5 db input gain/attenuation range: mic, line, aux, cd, video, phone_in, dac ?6.5 db step size (0 db to ?5 db): (all steps tested) pc_beep 3.0 db input gain/attenuation range: pc_beep ?5 db * guaranteed, not tested. specifications subject to change without notice. temperature 25 c digital supply (v dd ) 3.3 v analog supply (v cc ) 5.0 v sample rate (f s ) 48 khz input signal 1008 hz standard test conditions unless otherwise noted dac test conditions calibrated ? db attenuation relative to full-scale input 0 db 10 k ? output load adc test conditions calibrated 0 db gain input ?.0 db relative to full-scale
C3C rev. 0 AD1881A digital decimation and interpolation filters * parameter min typ max unit passband 0 0.4 f s hz passband ripple 0.09 db transition band 0.4 f s 0.6 f s hz stopband 0.6 f s hz stopband rejection ?4 db group delay 12/f s sec group delay variation over passband 0.0 s analog-to-digital converters parameter min typ max unit resolution 16 bits total harmonic distortion (thd) 0.02 % ?4 db dynamic range (?0 db input thd+n referenced to full scale, a-weighted) 87 db signal-to-intermodulation distortion * (ccif method) 85 db adc crosstalk * line inputs (input l, ground r, read r; input r, ground l, read l) ?00 ?0 db line_in to other ?0 ?5 db gain error (full-scale span relative to nominal input voltage) 10 % interchannel gain mismatch (difference of gain errors) 0.5 db adc offset error 10.5 mv digital-to-analog converters parameter min typ max unit resolution 16 bits total harmonic distortion (thd) line_out, lnlvl_out 0.02 % ?4 db dynamic range (?0 db input thd+n referenced to full scale, a-weighted) 90 db signal-to-intermodulation distortion * (ccif method) 85 db gain error (full-scale span relative to nominal input voltage) 10 % interchannel gain mismatch (difference of gain errors) 0.7 db dac crosstalk * (input l, zero r, measure r_out; input r, zero l, ?0 db measure l_out) total audible out-of-band energy (measured from 0.6 f s to 20 khz) * ?0 db analog output parameter min typ max unit full-scale output voltage 1v rms (line_out, lnlvl_out) 2.83 v p-p output impedance * 500 ? external load impedance * 10 k ? output capacitance * 15 pf external load capacitance 100 pf v ref 2.0 2.2 2.5 v v ref_out 2.2 v mute click (muted output minus unmuted midscale dac output) 5mv * guaranteed, not tested. specifications subject to change without notice.
C4C rev. 0 AD1881A?pecifications static digital specifications parameter min typ max unit high level input voltage (v ih ): digital inputs 0.65 dv dd v low level input voltage (v il ) 0.35 dv dd v high level output voltage (v oh ), i oh = 0.5 ma 0.9 dv dd v low level output voltage (v ol ), i ol = +0.5 ma 0.1 dv dd v input leakage current ?0 +10 a output leakage current ?0 +10 a power supply parameter min typ max unit power supply range ?analog 4.75 5.25 v power supply range ?digital (3.3 v) 3.0 3.6 v power dissipation ?5 v/3.3 v 280 mw analog supply current ?5 v 40 ma digital supply current ?3.3 v 23 ma power supply rejection (100 mv p-p signal @ 1 khz) * 40 db (at both analog and digital supply pins, both adcs and dacs) clock specifications * parameter min typ max unit input clock frequency 24.576 mhz recommended clock duty cycle 45 50 55 % power-down mode dv dd (3.3 v) av dd (5 v) parameter set bits typ typ unit adc pr0 17 30 ma dac pr1 17 26 ma adc and dac pr1, pr0 4 20 ma adc + dac + mixer (analog cd on) lpmix, pr1, pr0 4 12 ma mixer pr2 20 18 ma adc + mixer pr2, pr0 17 12 ma dac + mixer pr2, pr1 17 8 ma adc + dac + mixer pr2, pr1, pr0 4 2 ma analog cd only (ac-link on) lpmix, pr5, pr1, pr0 4 12 ma analog cd only (ac-link off) lpmix, pr1, pr0, pr4, pr5 0 12 ma standby pr5, pr4, pr3, pr2, pr1, pr0 0 0.1 ma * guaranteed, not tested. specifications subject to change without notice.
AD1881A C5C rev. 0 timing parameters 1 (guaranteed over operating temperature range) parameter symbol min typ max unit reset active low pulsewidth t rst_low 50 ns reset inactive to bit_clk startup delay t rst2clk 833 s sync active high pulsewidth t sync_high 80 ns sync low pulsewidth t sync_low 19.5 s sync inactive to bit_clk startup delay t sync2clk 162.8 ns bit_clk frequency 12.288 mhz bit_clk period t clk_period 81.4 ns bit_clk output jitter 2 750 ps bit_clk high pulsewidth t clk_high 36.62 40.69 44.76 ns bit_clk low pulsewidth t clk_low 36.62 40.69 44.76 ns sync frequency 48.0 khz sync period t sync_period 20.8 s setup to falling edge of bit_clk t setup 5 2.5 ns hold from falling edge of bit_clk t hold 5ns bit_clk rise time t riseclk 24 10ns bit_clk fall time t fallclk 24 10ns sync rise time t risesync 24 10ns sync fall time t fallsync 24 10ns sdata_in rise time t risedin 24 10ns sdata_in fall time t falldin 24 10ns sdata_out rise time t risedout 24 10ns sdata_out fall time t falldout 24 10ns end of slot 2 to bit_clk, sdata_in low t s2_pdown 010ms setup to trailing edge of reset (applies to sync, sdata_out) t setup2rst 15 ns rising edge of reset to hi-z delay (ate test mode) t off 25 ns propagation delay 15 ns reset rise time 50 ns notes 1 guaranteed, not tested. 2 output jitter is directly dependent on crystal input jitter. specifications subject to change without notice.
AD1881A C6C rev. 0 reset bit_clk t rst2clk t rst_low figure 1. cold reset sync bit_clk t sync_high t rst2clk figure 2. warm reset t clk_high bit_clk t clk_low sync t sync_high t sync_low t sync_period t clk_period figure 3. clock timing bit_clk sync t hold sdata_out t setup figure 4. data setup and hold bit_clk sync sdata_in t riseclk t risesync t risedin t risedout t fallclk t fallsync t falldin t falldout sdata_out figure 5. signal rise and fall time bit_clk sdata_out sync sdata_in slot 1 slot 2 write to 0x26 data pr4 don? care t s2_pdown note: bit_clk not to scale figure 6. ac link low power mode timing reset sdata_out hi-z t setup2rst t off sdata_in, bit_clk figure 7. ate test mode
AD1881A C7C rev. 0 absolute maximum ratings * parameter min max unit power supplies digital (v dd ) ?.3 +3.6 v analog (v cc ) ?.3 +6.0 v analog input voltage (signal pins) ?.3 v cc + 0.3 v digital input voltage (signal pins) ?.3 v dd + 0.3 v ambient temperature (operating) 0 +70 c storage temperature ?5 +150 c * stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in t he operational section of this specification is not implied. exposure to absolu te maximum rating conditions for extended periods may affect device reliability. ordering guide temperature package package model range description option AD1881Ajst 0 c to 70 c 48-lead lqfp st-48 environmental conditions ambient temperature rating t amb = t case ?(pd ca ) t case = case temperature in c p d = power dissipation in w ca = thermal resistance (case-to-ambient) ja = thermal resistance (junction-to-ambient) jc = thermal resistance (junction-to-case) package ja jc ca lqfp 76.2 c/w 17 c/w 59.2 c/w caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD1881A features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device pin configuration 48-lead lqfp 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 av ss2 eapd/chain_in lnlvl_out_r cs0 nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) line_out_r line_out_l cx3d rx3d filt_l filt_r afilt2 phone_in aux_l aux_r video_l cd_gnd_ref dv dd1 xtl_in xtl_out sdata_out bit_clk sdata_in sync reset pc_beep nc = no connect afilt1 cd_r mic1 mic2 line_in_l mono_out AD1881A line_in_r cs1 cd_l video_r mode dv ss1 dv ss2 dv dd2 vrefout vref av ss1 av dd1 av dd2 lnlvl_out_l
AD1881A C8C rev. 0 pin function descriptions digital i/o pin name lqfp i/o description xtl_in 2 i crystal (or clock) input, 24.576 mhz. xtl_out 3 o crystal output. sdata_out 5 i ac-link serial data output, AD1881A input stream. bit_clk 6 o ac-link bit clock. 12.288 mhz serial data clock. daisy chain output clock. sdata_in 8 o ac-link serial data input. AD1881A output stream. sync 10 i ac-link frame sample sync 48 khz fixed rate. reset 11 i ac-link reset. AD1881A master h/w reset. miscellaneous connections pin name lqfp i/o description cs0 45 i chip select 0. cs1 46 i chip select 1. eapd 47 o external amp power-down control signal, default lo, active hi mode 48 i mode select. analog i/o these signals connect the AD1881A component to analog sources and sinks, including microphones and speakers. pin name lqfp i/o description pc_beep 12 i pc beep. pc speaker beep passthrough. phone_in 13 i phone. from telephony subsystem speakerphone or handset. aux_l 14 i auxiliary input left channel. aux_r 15 i auxiliary input right channel. video_l 16 i video audio left channel. video_r 17 i video audio right channel. cd_l 18 i cd audio left channel. cd_gnd_ref 19 i cd audio analog ground reference for pseudo-differential cd input. cd_ r 20 i cd audio right channel. mic1 21 i microphone 1. desktop microphone input. mic2 22 i microphone 2. second microphone input. line_in_l 23 i line in left channel. line_in_r 24 i line in right channel. line_out_l 35 o line out left channel. line_out_r 36 o line out right channel. mono_out 37 o monaural output to telephony subsystem speakerphone. lnlvl_out_l 39 o line-level output left channel. lnlvl_out_r 41 o line-level output right channel. filter/reference these signals are connected to resistors, capacitors, or specific voltages. pin name lqfp i/o description vref 27 o voltage reference filter. vrefout 28 o voltage reference output 5 ma drive (intended for mic bias). afilt1 29 o antialiasing filter capacitor?dc right channel. afilt2 30 o antialiasing filter capacitor?dc left channel. filt_r 31 o ac-coupling filter capacitor?dc right channel. filt_l 32 o ac-coupling filter capacitor?dc left channel. rx3d 33 o 3d phat stereo enhancement?apacitor. cx3d 34 i 3d phat stereo enhancement?apacitor.
AD1881A C9C rev. 0 power and ground signals pin name lqfp type description dv dd1 1 i digital v dd 3.3 v dv ss1 4 i digital gnd dv ss2 7 i digital gnd dv dd2 9 i digital v dd 3.3 v av dd1 25 i analog v dd 5.0 v av ss1 26 i analog gnd av dd2 38 i analog v dd 5.0 v av ss2 42 i analog gnd no connects pin name lqfp type description nc 40 no connect nc 43 no connect nc 44 no connect 0x20 phat 0x22 dp 0 x 74 oscillators g = gain a = attenuate m = mute mv = master volume gm 0x1c rim im gm 0x1c lim im ls/rs (0) ls (4) rs (4) ls (3) rs (3) ls (1) rs (1) ls/rs (6) rs (5) ls (2) rs (2) s 0x1a s e l e c t o r ls/rs (7) ls (5) 0x20 pop m 0x14 vm m 0x16 cm m 0x12 am m 0x10 lm m 0x0e mcm reset sync bit_clk sdata_out sdata_in gm 0 x 1c lim im ga 0x14 lvv rvv ga 0x12 lcv rcv ga 0x16 lav rav ga 0x10 llv rla ga 0x0e mcv gam 0x18 lov om rov om gam 0x18 ac link gm 0 x 1c rim im 16-bit a/d 16-bit a/d 16-bit d/a 16-bit d/a lpbk 0x20 pcm dac rate 0x2c sr1 0x7a pcm adc rate 0x32 sr0 0x78 xtl_out xtl_in stereo mix (l) mono mix stereo mix (r) AD1881A m 0x0c phm ga 0x0c phv a 0x0a pcv m 0x0a pcm 0x02 mm 0x20 0x02 mm ms 0 1 dam 02 lmv line_out_l line_out_r pc_beep mic1 mic2 aux cd video 0db/20db m20 0x0e phone_in line_in lnlvl_out_l lnlvl_out_r 02 lmv 0x22 dp mv nc nc mix 0x20 0x20 phat pop 0x20 pop 0x20 mono_out figure 8. block diagram register map
AD1881A C10C rev. 0 product overview the AD1881A meets the audio codec ?7 2.0 and 2.1 extensions . in addition, the AD1881A soundmax codec is designed to meet all requirements of the audio codec ?7, component specification , revi- sion 1.03, ?1996, intel corporation, found at www.intel.com . the AD1881A also includes some other codec enhanced fea- tures such as the built-in phat stereo 3d enhancement. the AD1881A is an analog front end for high performance pc audio applications. the ac?7 architecture defines a 2-chip audio solution comprising a digital audio controller, plus a high quality analog component that includes digital-to-analog converters (dacs), analog-to-digital converters (adcs), mixer and i/o. the main architectural features of the AD1881A are the high quality analog mixer section, two channels of ? adc conversion, two channels of ? dac conversion with data direct scram- bling (d 2 s) rate generators. the AD1881A? left channel adc and dac are compatible for modem applications supporting irra- tional sample rates and modem filtering requirements. functional description this section overviews the functionality of the AD1881A and is intended as a general introduction to the capabilities of the device. detailed reference information may be found in the descriptions of the indexed control registers. analog inputs the codec contains a stereo pair of ? adcs. inputs to the adc may be selected from the following analog signals: tele- phony (phone_in), mono microphone (mic1 or mic2), stereo line (line_in), auxiliary line input (aux), stereo cd rom (cd), stereo audio from a video source (video) and post-mixed stereo or mono line output (line_out). analog mixing phone_in, mic1 or mic2, line_in, aux, cd and video can be mixed in the analog domain with the stereo output from the dacs. each channel of the stereo analog inputs may be inde- pendently gained or attenuated from +12 db to ?4.5 db in 1.5 db steps. the summing path for the mono in puts (phone_in, mic1, and mic2 to line_out) duplicates mono channel data on both the left and right line_out. additionally, the pc attention sig- nal (pc_beep) may be mixed with the line output. a switch allows the output of the dacs to bypass the phat stereo 3d enhancement. digital audio mode the AD1881A is designed with a digital audio mode (dam) that allows mixing of all analog inputs independent of the dac output signal path. mixed analog input signals may be sent to the adcs for processing by the controller or the host, and may be used during simultaneous capture and playback at different sample rates. analog-to-digital signal path the selector sends left and right channel information to the programmable gain amplifier (pga). the pga following the selector allows independent gain control for each channel ente ring the adc from 0 db to +22.5 db in 1.5 db steps. each channel of the adc is independent, and can process left and right chan- nel data at different sample rates. sample rates and d 2 s the AD1881A default mode sets the codec to operate at 48 khz sample rates. the converter pairs may process left and right channel data at different sample rates. the AD1881A sample rate generator allows the codec to instantaneously change and proc ess sample rates from 8 khz to 48 khz with a resolution of 1 hz. the in-band integrated noise and distortion artifacts introduced by rate conversions are below ?0 db. the AD1881A uses a 4-bit d/a structure and data directed scrambling (d 2 s) to enhance noise immunity on motherboards and in pc enclo- sures, and to suppress idle tones below the device? quantization noise floor. the d 2 s process pushes noise and distortion artifacts caused by errors in the multibit dac to frequencies beyond the auditory response of the human ear and then filters them. digital-to-analog signal path the analog output of the dac may be gained or attenuated from +12 db to ?4.5 db in 1.5 db steps, and summed with any of the analog input signals. the summed analog signal enters the master volume stage where each channel of the mixer output may be attenuated from 0 db to ?4.5 db in 1.5 db steps or muted. line-level outputs the AD1881A offers a true line-level output for notebook dock- ing station and home theater applications. the line-level output does not change with master volume settings. host-based echo cancellation support the AD1881A supports time correlated i/o data format by pre- senting mic data on the left channel of the adc and the mono summation of left and right output on the right channel. the adc is splittable; left and right adc data can be sampled at different rates. power management modes the AD1881A is designed to meet acpi power consumption requirements through flexible power management control of all internal resources.
AD1881A C11C rev. 0 indexed control registers reg num name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 00h reset x se4 se3 se2 se1 se0 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 0410h 02h master volume mm x lmv5 lmv4 lmv3 lmv2 lmv1 lmv0 x x rmv5 rmv4 rmv3 rmv2 rmv1 rmv0 8000h 04h reserved x xxxxxxxxxxxxxxx x 06h master volume mono mmm xxxxxxxxxxmmvmmvmmvmmvmmv 8000h 42210 08h reserved x xxxxxxxxxxxxxxx x 0ah pc beep volume pcm xxxxxxxxxx pcv3 pcv2 pcv1 pcv0 x 8000h 0ch phone in volume phm xxxxxxxxxx phv4 phv3 phv2 phv1 phv0 8008h 0eh mic volume mcm xxxxxxxxm20x mcv4 mcv3 mcv2 mcv1 mcv0 8008h 10h line in volume lm x x llv4 llv3 llv2 llv1 llv0 x x x rlv4 rlv3 rlv2 rlv1 rlv0 8808h 12h cd volume cvm x x lcv4 lcv3 lcv2 lcv1 lcv0 x x x rcv4 rcv3 rcv2 rcv1 rcv0 8808h 14h video volume vm x x lvv4 lvv3 lvv2 lvv1 lvv0 x x x rvv4 rvv3 rvv2 rvv1 rvv0 8808h 16h aux volume am x x lav4 lav3 lav2 lav1 lav0 x x x rav4 rav3 rav2 rav1 rav0 8808h 18h pcm out vol om x x lov4 lov3 lov2 lov1 lov0 x x x rov4 rov3 rov2 rov1 rov0 8808h 1ah record select x xxxxls2ls1ls0xxxxxrs2rs1rs0 0000h 1ch record gain im x x x lim3 lim2 lim1 lim0 xxxx rim3 rim2 rim1 rim0 8000h 1eh reserved x xxxxxxxxxxxxxxx x 20h general purpose pop x 3d x x x mix ms lpbk xxxxxxx 0000h 22h 3d control x xxxxxxxxxxxdp3dp2dp1dp0 0000h 26h power-down cntrl/stat eapd x pr5 pr4 pr3 pr2 pr1 pr0 xxxxrefanldacadc 000xh 28h extended audio id id1 id0 xxxxxxxxxxxxxvra 0001h 2ah extended audio stat/ctrl x xxxxxxxxxxxxxxvra 0000h 2ch/ pcm dac rate (sr1) sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h (7ah) * 32h / pcm adc rate (sr0) sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h (78h) * 34h reserved x xxxxxxxxxxxxxxx x 5ah vendor reserved ** .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 70h 72h reserved x xxxxxxxxxxxxxxx x 74h serial configuration slot xxxxxxxxxxxxxxx 7x0xh 16 76h misc. control bits dac lpmi x dam dms dlsr x alsr mod srx srx x x drsr x arsr 0404h z x en 10d7 8d7 7ch vendor id1 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 4144h 7eh vendor id2 t7 t6 t5 t4 t3 t2 t1 t0 rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 5348h notes all registers not shown and bits containing an x are assumed to be reserved. odd register addresses are aliased to the next lower even address. reserved registers should not be written. zeros should be written to reserved bits. * indicates aliased register for ad1819, ad1819a backward compatibility. ** vendor reserved registers should not be written.
AD1881A C12C rev. 0 reset (index 00h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 0 0h 0 0 h 0 0 h 0 0h 0 0t e s e rt e s e r t e s e r t e s e rt e s e rx x x x x4 e s4 e s 4 e s 4 e s4 e s3 e s3 e s 3 e s 3 e s3 e s2 e s2 e s 2 e s 2 e s2 e s1 e s1 e s 1 e s 1 e s1 e s0 e s0 e s 0 e s 0 e s0 e s9 d i9 d i 9 d i 9 d i9 d i8 d i8 d i 8 d i 8 d i8 d i7 d i7 d i 7 d i 7 d i7 d i6 d i6 d i 6 d i 6 d i6 d i5 d i5 d i 5 d i 5 d i5 d i4 d i4 d i 4 d i 4 d i4 d i3 d i3 d i 3 d i 3 d i3 d i2 d i2 d i 2 d i 2 d i2 d i1 d i1 d i 1 d i 1 d i1 d i0 d i0 d i 0 d i 0 d i0 d ih 0 1 4 0h 0 1 4 0 h 0 1 4 0 h 0 1 4 0h 0 1 4 0 note: writing any value to this register per forms a register reset, which causes all registers to revert to their default values (except 74h, which forces the serial configuration). reading this register returns the id code of the part and a code for the type of 3 d stereo enhancement. id[9:0] identify capability. the id decodes the capabilities of AD1881A based on the following: bit = 1 function AD1881A id0 dedicated mic pcm in channel 0 id1 modem line codec support 0 id2 bass and treble control 0 id3 simulated stereo (mono to stereo) 0 id4 headphone out/true line-level out 1 id5 loudness (bass boost) support 0 id6 18-bit dac resolution 0 id7 20-bit dac resolution 0 id8 18-bit adc resolution 0 id9 20-bit adc resolution 0 se[4:0] stereo enhancement. the 3d stereo enhancement identifies the analog devices 3d stereo enhancement. master volume registers (index 02h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 2 0h 2 0 h 2 0 h 2 0h 2 0 r e t s a mr e t s a m r e t s a m r e t s a mr e t s a m e m u l o ve m u l o v e m u l o v e m u l o ve m u l o v m mm m m m m mm mx x x x x5 v m l5 v m l 5 v m l 5 v m l5 v m l4 v m l4 v m l 4 v m l 4 v m l4 v m l3 v m l3 v m l 3 v m l 3 v m l3 v m l2 v m l2 v m l 2 v m l 2 v m l2 v m l1 v m l1 v m l 1 v m l 1 v m l1 v m l0 v m l0 v m l 0 v m l 0 v m l0 v m lx x x x xx x x x x5 v m r5 v m r 5 v m r 5 v m r5 v m r4 v m r4 v m r 4 v m r 4 v m r4 v m r3 v m r3 v m r 3 v m r 3 v m r3 v m r2 v m r2 v m r 2 v m r 2 v m r2 v m r1 v m r1 v m r 1 v m r 1 v m r1 v m r0 v m r0 v m r 0 v m r 0 v m r0 v m rh 0 0 0 8h 0 0 0 8 h 0 0 0 8 h 0 0 0 8h 0 0 0 8 rmv[5:0] right master volume control. the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of ?4.5 db. lmv[5:0] l eft master volume control. the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of ?4.5 db. mm master volume mute. when this bit is set to ?,?the channel is muted. mm xmv5 . . . xmv0 function 0 00 0000 0 db attenuation 0 01 1111 ?6.5 db attenuation 0 11 1111 ?4.5 db attenuation 1 xx xxxx db attenuation master volume mono (index 06h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 6 0h 6 0 h 6 0 h 6 0h 6 0 e m u l o v r e t s a me m u l o v r e t s a m e m u l o v r e t s a m e m u l o v r e t s a me m u l o v r e t s a m o n o mo n o m o n o m o n o mo n o m m m mm m m m m m m m mm m mx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x x4 v m m4 v m m 4 v m m 4 v m m4 v m m3 v m m3 v m m 3 v m m 3 v m m3 v m m2 v m m2 v m m 2 v m m 2 v m m2 v m m1 v m m1 v m m 1 v m m 1 v m m1 v m m0 v m m0 v m m 0 v m m 0 v m m0 v m mh 0 0 0 8h 0 0 0 8 h 0 0 0 8 h 0 0 0 8h 0 0 0 8 mmv[4:0] mono master volume control. the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of ?6.5 db. mmm mono master volume mute. when this bit is set to ?,?the channel is muted.
AD1881A C13C rev. 0 pc beep register (index 0ah) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h a 0h a 0 h a 0 h a 0h a 0e m u l o v p e e b _ c pe m u l o v p e e b _ c p e m u l o v p e e b _ c p e m u l o v p e e b _ c pe m u l o v p e e b _ c pm c pm c p m c p m c pm c px x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x x3 v c p3 v c p 3 v c p 3 v c p3 v c p2 v c p2 v c p 2 v c p 2 v c p2 v c p1 v c p1 v c p 1 v c p 1 v c p1 v c p0 v c p0 v c p 0 v c p 0 v c p0 v c px x x x xh 0 0 0 8h 0 0 0 8 h 0 0 0 8 h 0 0 0 8h 0 0 0 8 pcv[3:0] pc beep volume control. the least significant bit represents 3 db attenuation. this register controls the output from 0 db to a maximum attenuation of ?5 db. the pc beep is routed to left and right line outputs even when the reset pin is asserted. this is so that power on self-test (post) codes can be heard by the user in case of a hardware problem with the pc. pcm pc beep mute. when this bit is set to ?,?the channel is muted. pcm pcv3 . . . pcv0 function 0 0000 0 db attenuation 0 1111 ?5 db attenuation 1 xxxx db attenuation phone volume (index 0ch) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h c 0h c 0 h c 0 h c 0h c 0e m u l o v e n o h pe m u l o v e n o h p e m u l o v e n o h p e m u l o v e n o h pe m u l o v e n o h pm h pm h p m h p m h pm h px x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x x4 v h p4 v h p 4 v h p 4 v h p4 v h p3 v h p3 v h p 3 v h p 3 v h p3 v h p2 v h p2 v h p 2 v h p 2 v h p2 v h p1 v h p1 v h p 1 v h p 1 v h p1 v h p0 v h p0 v h p 0 v h p 0 v h p0 v h ph 8 0 0 8h 8 0 0 8 h 8 0 0 8 h 8 0 0 8h 8 0 0 8 phv[4:0] phone volume. allows setting the phone volume attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. phm phone mute. when this bit is set to ?,?the channel is muted. mic volume (index 0eh) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h e 0h e 0 h e 0 h e 0h e 0e m u l o v c i me m u l o v c i m e m u l o v c i m e m u l o v c i me m u l o v c i mm c mm c m m c m m c mm c mx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x x0 2 m0 2 m 0 2 m 0 2 m0 2 mx x x x x4 v c m4 v c m 4 v c m 4 v c m4 v c m3 v c m3 v c m 3 v c m 3 v c m3 v c m2 v c m2 v c m 2 v c m 2 v c m2 v c m1 v c m1 v c m 1 v c m 1 v c m1 v c m0 v c m0 v c m 0 v c m 0 v c m0 v c mh 8 0 0 8h 8 0 0 8 h 8 0 0 8 h 8 0 0 8h 8 0 0 8 mcv[4:0] mic volume gain. allows setting the mic volume attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. m20 microphone 20 db gain block 0 = disabled; gain = 0 db. 1 = enabled; gain = 20 db. mcm mic mute. when this bit is set to ?,?the channel is muted. line in volume (index 10h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 0 1h 0 1 h 0 1 h 0 1h 0 1e m u l o v n i e n i le m u l o v n i e n i l e m u l o v n i e n i l e m u l o v n i e n i le m u l o v n i e n i lm lm l m l m lm lx x x x xx x x x x4 v l l4 v l l 4 v l l 4 v l l4 v l l3 v l l3 v l l 3 v l l 3 v l l3 v l l2 v l l2 v l l 2 v l l 2 v l l2 v l l1 v l l1 v l l 1 v l l 1 v l l1 v l l0 v l l0 v l l 0 v l l 0 v l l0 v l lx x x x xx x x x xx x x x x4 v l r4 v l r 4 v l r 4 v l r4 v l r3 v l r3 v l r 3 v l r 3 v l r3 v l r2 v l r2 v l r 2 v l r 2 v l r2 v l r1 v l r1 v l r 1 v l r 1 v l r1 v l r0 v l r0 v l r 0 v l r 0 v l r0 v l rh 8 0 8 8h 8 0 8 8 h 8 0 8 8 h 8 0 8 8h 8 0 8 8 rlv[4:0] right line in volume. allows setting the line in right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. llv[4:0] line in volume left. allows setting the line in left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. lm line in mute. when this bit is set to ?,?the channel is muted.
AD1881A C14C rev. 0 cd volume (index 12h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 2 1h 2 1 h 2 1 h 2 1h 2 1e m u l o v d ce m u l o v d c e m u l o v d c e m u l o v d ce m u l o v d cm v cm v c m v c m v cm v cx x x x xx x x x x4 v c l4 v c l 4 v c l 4 v c l4 v c l3 v c l3 v c l 3 v c l 3 v c l3 v c l2 v c l2 v c l 2 v c l 2 v c l2 v c l1 v c l1 v c l 1 v c l 1 v c l1 v c l0 v c l0 v c l 0 v c l 0 v c l0 v c lx x x x xx x x x xx x x x x4 v c r4 v c r 4 v c r 4 v c r4 v c r3 v c r3 v c r 3 v c r 3 v c r3 v c r2 v c r2 v c r 2 v c r 2 v c r2 v c r1 v c r1 v c r 1 v c r 1 v c r1 v c r0 v c r0 v c r 0 v c r 0 v c r0 v c rh 8 0 8 8h 8 0 8 8 h 8 0 8 8 h 8 0 8 8h 8 0 8 8 rcv[4:0] right cd volume. allows setting the cd right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. lcv[4:0] left cd volume. allows setting the cd left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. cvm cd volume mute. when this bit is set to ?,?the channel is muted. video volume (index 14h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 4 1h 4 1 h 4 1 h 4 1h 4 1e m u l o v o e d i ve m u l o v o e d i v e m u l o v o e d i v e m u l o v o e d i ve m u l o v o e d i vm vm v m v m vm vx x x x xx x x x x4 v v l4 v v l 4 v v l 4 v v l4 v v l3 v v l3 v v l 3 v v l 3 v v l3 v v l2 v v l2 v v l 2 v v l 2 v v l2 v v l1 v v l1 v v l 1 v v l 1 v v l1 v v l0 v v l0 v v l 0 v v l 0 v v l0 v v lx x x x xx x x x xx x x x x4 v v r4 v v r 4 v v r 4 v v r4 v v r3 v v r3 v v r 3 v v r 3 v v r3 v v r2 v v r2 v v r 2 v v r 2 v v r2 v v r1 v v r1 v v r 1 v v r 1 v v r1 v v r0 v v r0 v v r 0 v v r 0 v v r0 v v rh 8 0 8 8h 8 0 8 8 h 8 0 8 8 h 8 0 8 8h 8 0 8 8 rvv[4:0] right video volume. allows setting the video right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. lvv[4:0] left video volume. allows setting the video left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. vm video mute. when this bit is set to ?,?the channel is muted. aux volume (index 16h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 6 1h 6 1 h 6 1 h 6 1h 6 1e m u l o v x u ae m u l o v x u a e m u l o v x u a e m u l o v x u ae m u l o v x u am am a m a m am ax x x x xx x x x x4 v a l4 v a l 4 v a l 4 v a l4 v a l3 v a l3 v a l 3 v a l 3 v a l3 v a l2 v a l2 v a l 2 v a l 2 v a l2 v a l1 v a l1 v a l 1 v a l 1 v a l1 v a l0 v a l0 v a l 0 v a l 0 v a l0 v a lx x x x xx x x x xx x x x x4 v a r4 v a r 4 v a r 4 v a r4 v a r3 v a r3 v a r 3 v a r 3 v a r3 v a r2 v a r2 v a r 2 v a r 2 v a r2 v a r1 v a r1 v a r 1 v a r 1 v a r1 v a r0 v a r0 v a r 0 v a r 0 v a r0 v a rh 8 0 8 8h 8 0 8 8 h 8 0 8 8 h 8 0 8 8h 8 0 8 8 rav[4:0] right aux. volume. allows setting the aux right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. lav[4:0] left aux. volume. allows setting the aux left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. am aux. mute. when this bit is set to ?,?the channel is muted. pcm out volume (index 18h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 8 1h 8 1 h 8 1 h 8 1h 8 1 t u o m c pt u o m c p t u o m c p t u o m c pt u o m c p e m u l o ve m u l o v e m u l o v e m u l o ve m u l o v m om o m o m om ox x x x xx x x x x4 v o l4 v o l 4 v o l 4 v o l4 v o l3 v o l3 v o l 3 v o l 3 v o l3 v o l2 v o l2 v o l 2 v o l 2 v o l2 v o l1 v o l1 v o l 1 v o l 1 v o l1 v o l0 v o l0 v o l 0 v o l 0 v o l0 v o lx x x x xx x x x xx x x x x4 v o r4 v o r 4 v o r 4 v o r4 v o r3 v o r3 v o r 3 v o r 3 v o r3 v o r2 v o r2 v o r 2 v o r 2 v o r2 v o r1 v o r1 v o r 1 v o r 1 v o r1 v o r0 v o r0 v o r 0 v o r 0 v o r0 v o rh 8 0 8 8h 8 0 8 8 h 8 0 8 8 h 8 0 8 8h 8 0 8 8 rov[4:0] right pcm out volume. allows setting the pcm right channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. lov[4:0] left pcm out volume. allows setting the pcm left channel attenuator in 32 steps. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. om pcm out volume mute. when this bit is set to ?,?the channel is muted. volume table (index 0ch to 18h) mm x4 . . . x0 function 0 00000 +12 db gain 0 01000 0 db gain 0 11111 ?4.5 db gain 1 xxxxx db gain
AD1881A C15C rev. 0 record select control register (index 1ah) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h a 1h a 1 h a 1 h a 1h a 1t c e l e s d r o c e rt c e l e s d r o c e r t c e l e s d r o c e r t c e l e s d r o c e rt c e l e s d r o c e rx x x x xx x x x xx x x x xx x x x xx x x x x2 s l2 s l 2 s l 2 s l2 s l1 s l1 s l 1 s l 1 s l1 s l0 s l0 s l 0 s l 0 s l0 s lx x x x xx x x x xx x x x xx x x x xx x x x x2 s r2 s r 2 s r 2 s r2 s r1 s r1 s r 1 s r 1 s r1 s r0 s r0 s r 0 s r 0 s r0 s rh 0 0 0 0h 0 0 0 0 h 0 0 0 0 h 0 0 0 0h 0 0 0 0 rs[2:0] right record select ls[2:0] left record select. used to select the record source independently for right and left. see table for legend. the default value is 0000h, which corresponds to mic in. rs2 . . . rs0 right record source 0 mic 1 cd_r 2 video_r 3 aux_r 4 line_in_r 5 stereo mix (r) 6 mono mix 7 phone_in ls2 . . . ls0 left record source 0 mic 1 cd_l 2 video_l 3 aux_l 4 line_in_l 5 stereo mix (l) 6 mono mix 7 phone_in record gain (index 1ch) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h c 1h c 1 h c 1 h c 1h c 1n i a g d r o c e rn i a g d r o c e r n i a g d r o c e r n i a g d r o c e rn i a g d r o c e rm im i m i m im ix x x x xx x x x xx x x x x3 m i l3 m i l 3 m i l 3 m i l3 m i l2 m i l2 m i l 2 m i l 2 m i l2 m i l1 m i l1 m i l 1 m i l 1 m i l1 m i l0 m i l0 m i l 0 m i l 0 m i l0 m i lx x x x xx x x x xx x x x xx x x x x3 m i r3 m i r 3 m i r 3 m i r3 m i r2 m i r2 m i r 2 m i r 2 m i r2 m i r1 m i r1 m i r 1 m i r 1 m i r1 m i r0 m i r0 m i r 0 m i r 0 m i r0 m i rh 0 0 0 8h 0 0 0 8 h 0 0 0 8 h 0 0 0 8h 0 0 0 8 rim[3:0] right input mixer gain control. each lsb represents 1.5 db, 0000 = 0 db and the range is 0 db to +22.5 db. lim[3:0] left input mixer gain control. each lsb represents 1.5 db, 0000 = 0 db and the range is 0 db to +22.5 db. im input mute. 0 = unmuted, 1 = muted or db gain. im xim3 . . . xim0 function 0 1111 +22.5 db gain 0 0000 0 db gain 1 xxxxx db gain
AD1881A C16C rev. 0 general purpose register (index 20h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 0 2h 0 2 h 0 2 h 0 2h 0 2e s o p r u p l a r e n e ge s o p r u p l a r e n e g e s o p r u p l a r e n e g e s o p r u p l a r e n e ge s o p r u p l a r e n e gp o pp o p p o p p o pp o px x x x xd 3d 3 d 3 d 3d 3x x x x xx x x x xx x x x xx i mx i m x i m x i mx i ms ms m s m s ms mk b p lk b p l k b p l k b p lk b p lx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xh 0 0 0 0h 0 0 0 0 h 0 0 0 0 h 0 0 0 0h 0 0 0 0 note: this register should be read before writing to generate a mask for only the bit(s) that need to be changed. the function default v alue is 0000h which is all off. lpbk loopback control. adc/dac digital loopback mode ms mic select 0 = mic1. 1 = mic2. mix mono output select 0 = mix. 1 = mic. 3d 3d phat stereo enhancement 0 = phat stereo is off. 1 = phat stereo is on. pop pcm output path and mute. the pop bit controls the optional pcm out 3d bypass path (the pre- and post-3d pcm out paths are mutually exclusive). 0 = pre-3d. 1 = post-3d. 3d control register (index 22h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 2 2h 2 2 h 2 2 h 2 2h 2 2l o r t n o c d 3l o r t n o c d 3 l o r t n o c d 3 l o r t n o c d 3l o r t n o c d 3x x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x x3 p d3 p d 3 p d 3 p d3 p d2 p d2 p d 2 p d 2 p d2 p d1 p d1 p d 1 p d 1 p d1 p d0 p d0 p d 0 p d 0 p d0 p dh 0 0 0 0h 0 0 0 0 h 0 0 0 0 h 0 0 0 0h 0 0 0 0 dp[2:0] depth control. sets 3d ?epth?phat stereo enhancement according to table below. dp3 . . . dp0 depth 0000 0% 0001 6.67% .. .. 1110 93.33% 1111 100%
AD1881A C17C rev. 0 subsection ready register (index 26h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 6 2h 6 2 h 6 2 h 6 2h 6 2t a t s / l r t n c n w o d - r e w o pt a t s / l r t n c n w o d - r e w o p t a t s / l r t n c n w o d - r e w o p t a t s / l r t n c n w o d - r e w o pt a t s / l r t n c n w o d - r e w o pd p a ed p a e d p a e d p a ed p a ex x x x x5 r p5 r p 5 r p 5 r p5 r p4 r p4 r p 4 r p 4 r p4 r p3 r p3 r p 3 r p 3 r p3 r p2 r p2 r p 2 r p 2 r p2 r p1 r p1 r p 1 r p 1 r p1 r p0 r p0 r p 0 r p 0 r p0 r px x x x xx x x x xx x x x xx x x x xf e rf e r f e r f e rf e rl n al n a l n a l n al n ac a dc a d c a d c a dc a dc d ac d a c d a c d ac d aa / na / n a / n a / na / n note: the ready bits are read only, writing to ref, anl, dac, adc will have no effect. these bits indicate the status for the AD1881A subsections. if the bit is a one, then that subsection is ready .?ready is defined as the subsection able to perform in its nominal state. adc adc section ready to transmit data. dac dac section ready to accept data. anl analog gain, attenuators and mute blocks, and mixers ready. ref voltage references, vref and vrefout up to nominal level. pr[5:0] AD1881A power-down modes. the first three bits are to be used individually rather than in combinat ion with each other. the last bit pr3 can be used in combination with pr2 or by itself. the mixer and reference cannot be powered down via pr3 unless the adcs and dacs are also powered down. nothing else can be powered up until the reference is up. pr5 has no effect unless all adcs, dacs, and the ac-link are powered down. the reference and the mixer can either be up or down, but all power-up sequences must be allowed to run to completion before pr5 and pr4 are both set. in multiple-codec systems, the master codec? pr5 and pr4 bits control the slave codec. pr5 is also effective in the slave codec if the master? pr5 bit is clear, but the pr4 bit has no effect except to enable or disable pr5. eapd external audio amp power down. available when programmed as an ac?7 codec. 0 = pin 47 set to lo state (default). 1 = pin 47 set to hi state. power-down state pr5 pr4 pr3 pr2 pr1 pr0 adc power-down 0 0 0 0 0 1 dac power-down 0 0 0 0 1 0 adc and dac power-down 0 0 0 0 1 1 mixer power-down 0 0 0 1 0 0 adc + mixer power-down 0 0 0 1 0 1 dac + mixer power-down 0 0 0 1 1 0 adc + dac + mixer power-down 0 0 0 1 1 1 standby 1 1 1 1 1 1 extended audio id register (index 28h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 8 2h 8 2 h 8 2 h 8 2h 8 2d i o i d u a d e d n e t x ed i o i d u a d e d n e t x e d i o i d u a d e d n e t x e d i o i d u a d e d n e t x ed i o i d u a d e d n e t x e1 d i1 d i 1 d i 1 d i1 d i0 d i0 d i 0 d i 0 d i0 d ix x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xa r va r v a r v a r va r vh 0 0 0 0h 0 0 0 0 h 0 0 0 0 h 0 0 0 0h 0 0 0 0 note: the extended audio id is a read only register. vra variable rate audio. vra = 1 enables variable rate audio. id[1:0] id1, id0 is a 2-bit field that indicates the codec configuration: primary is 00; secondary is 01, 10, or 11.
AD1881A C18C rev. 0 extended audio status and control register (index 2ah) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h a 2h a 2 h a 2 h a 2h a 2l r t c / t s o i d u a d e d n e t x el r t c / t s o i d u a d e d n e t x e l r t c / t s o i d u a d e d n e t x e l r t c / t s o i d u a d e d n e t x el r t c / t s o i d u a d e d n e t x ex x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xa r va r v a r v a r va r vh 0 0 0 0h 0 0 0 0 h 0 0 0 0 h 0 0 0 0h 0 0 0 0 note: the extended audio status and control register is a read/write register that provides status and control of the extended audio features. vra variable rate audio. vra = 1 enables variable rate audio mode (sample rate control registers and slotreq signaling. pcm dac rate register (index 2ch) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d ) h a 7 ( / h c 2) h a 7 ( / h c 2 ) h a 7 ( / h c 2 ) h a 7 ( / h c 2) h a 7 ( / h c 2e t a r c a d m c pe t a r c a d m c p e t a r c a d m c p e t a r c a d m c pe t a r c a d m c p5 1 r s5 1 r s 5 1 r s 5 1 r s5 1 r s4 1 r s4 1 r s 4 1 r s 4 1 r s4 1 r s3 1 r s3 1 r s 3 1 r s 3 1 r s3 1 r s2 1 r s2 1 r s 2 1 r s 2 1 r s2 1 r s1 1 r s1 1 r s 1 1 r s 1 1 r s1 1 r s0 1 r s0 1 r s 0 1 r s 0 1 r s0 1 r s9 r s9 r s 9 r s 9 r s9 r s8 r s8 r s 8 r s 8 r s8 r s7 r s7 r s 7 r s 7 r s7 r s6 r s6 r s 6 r s 6 r s6 r s5 r s5 r s 5 r s 5 r s5 r s4 r s4 r s 4 r s 4 r s4 r s3 r s3 r s 3 r s 3 r s3 r s2 r s2 r s 2 r s 2 r s2 r s1 r s1 r s 1 r s 1 r s1 r s0 r s0 r s 0 r s 0 r s0 r sh 0 8 b bh 0 8 b b h 0 8 b b h 0 8 b bh 0 8 b b note: 2ch is an alias for 7ah. the vra bit in register 2ah must be set for the alias to work; if a zero is written to vra, both sample rates are reset to 48k. sr[15:0] writing to this register allows programming of the sampling frequency from 8 khz (1b80h) to 48 khz (bb80h) in 1 hz increments. programming a value outside of the range 7040 hz (1b80h) to 48000 hz (bb80h) causes the codec to saturate to 48 khz if a rate greater than 48 khz is programmed or to 7.040 khz if a rate less than 7.040 khz is programmed. for all rates, if the value writ ten to the register is supported, that value will be echoed back when read, otherwise the closest rate supported is returned. pcm adc rate register (index 32h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d ) h 8 7 ( / h 2 3) h 8 7 ( / h 2 3 ) h 8 7 ( / h 2 3 ) h 8 7 ( / h 2 3) h 8 7 ( / h 2 3e t a r c d a m c pe t a r c d a m c p e t a r c d a m c p e t a r c d a m c pe t a r c d a m c p5 1 r s5 1 r s 5 1 r s 5 1 r s5 1 r s4 1 r s4 1 r s 4 1 r s 4 1 r s4 1 r s3 1 r s3 1 r s 3 1 r s 3 1 r s3 1 r s2 1 r s2 1 r s 2 1 r s 2 1 r s2 1 r s1 1 r s1 1 r s 1 1 r s 1 1 r s1 1 r s0 1 r s0 1 r s 0 1 r s 0 1 r s0 1 r s9 r s9 r s 9 r s 9 r s9 r s8 r s8 r s 8 r s 8 r s8 r s7 r s7 r s 7 r s 7 r s7 r s6 r s6 r s 6 r s 6 r s6 r s5 r s5 r s 5 r s 5 r s5 r s4 r s4 r s 4 r s 4 r s4 r s3 r s3 r s 3 r s 3 r s3 r s2 r s2 r s 2 r s 2 r s2 r s1 r s1 r s 1 r s 1 r s1 r s0 r s0 r s 0 r s 0 r s0 r sh 0 8 b bh 0 8 b b h 0 8 b b h 0 8 b bh 0 8 b b note: 32h is an alias for 78h. the vra bit in register 2ah must be set for the alias to work; if a zero is written to vra, both sample rates are reset to 48k. sr[15:0] writing to this register allows programming of the sampling frequency from 8 khz (1b80) to 48 khz (bb80h) in 1 hz increments. programming a value outside of the range 7040 hz (1b80h) to 48000 hz (bb80h) causes the codec to saturate to 48 khz if a rate greater than 48 khz is programmed, or to 7.040 khz if a rate less than 7.040 khz is programmed. for all rates, if the value written to the register is supported, that value will be echoed back when read, otherwise the closest rate supported is returned. serial configuration (index 74h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 4 7h 4 7 h 4 7 h 4 7h 4 7 l a i r e sl a i r e s l a i r e s l a i r e sl a i r e s n o i t a r u g i f n o cn o i t a r u g i f n o c n o i t a r u g i f n o c n o i t a r u g i f n o cn o i t a r u g i f n o c t o l st o l s t o l s t o l st o l s 6 16 1 6 1 6 16 1 x x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xx x x x xh x 0 x 7h x 0 x 7 h x 0 x 7 h x 0 x 7h x 0 x 7 note: this register is not reset when the reset register (register 00h) is written. slot16 enable 16-bit slots. drqen and dxrqx are retained only for compatibility with the ad1819. new controller designs should use the vra bit in register 2ah and the request bits in the status address slot instead. if your system uses only a single AD1881A, you can ignore the register mask and the slave 1/slave 2 request bits. if you write to this register, write ones to all of the register mask bits. slot16 makes all ac link slots 16 bits in length, formatted into 16 slots.
AD1881A C19C rev. 0 miscellaneous control bits (index 76h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 6 7h 6 7 h 6 7 h 6 7h 6 7s t i b l o r t n o c c s i ms t i b l o r t n o c c s i m s t i b l o r t n o c c s i m s t i b l o r t n o c c s i ms t i b l o r t n o c c s i m c a dc a d c a d c a dc a d z z z z z i m p li m p l i m p l i m p li m p l x x x x x x x x x xm a dm a d m a d m a dm a ds m ds m d s m d s m ds m dr s l dr s l d r s l d r s l dr s l dx x x x xr s l ar s l a r s l a r s l ar s l a d o md o m d o m d o md o m n en e n e n en e 0 1 x r s0 1 x r s 0 1 x r s 0 1 x r s0 1 x r s 7 d7 d 7 d 7 d7 d 8 x r s8 x r s 8 x r s 8 x r s8 x r s 7 d7 d 7 d 7 d7 d x x x x xx x x x xr s r dr s r d r s r d r s r dr s r dx x x x xr s r ar s r a r s r a r s r ar s r ah 4 0 4 0h 4 0 4 0 h 4 0 4 0 h 4 0 4 0h 4 0 4 0 arsr adc right sample generator select 0 = sr0 selected (32h) 1 = sr1 selected (2ch). drsr dac right sample generator select 0 = sr0 selected (32h) 1 = sr1 selected (2ch). srx8d7 multiply sr1 rate by 8/7. srx10d7 multiply sr1 rate by 10/7. srx10d7 and srx8d7 are mutually exclusive; srx10d7 has priority if both are set. moden modem filter enable (left channel only). change only when dacs are powered down. alsr adc left sample generator select 0 = sr0 selected (32h) 1 = sr1 selected (2ch). dlsr dac left sample generator select 0 = sr0 selected (32h) 1 = sr1 selected (2ch). dms digital mono select. 0 = mixer 1 = left dac and right dac. dam digital audio mode. dac outputs bypass analog mixer and sent directly to the codec output. lpmix low power mixer. keeps cd to line_out alive for notebook applications. dacz zero fill (vs. repeat) if dac is starved for data. sample rate 0 (index 78h) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h 8 7h 8 7 h 8 7 h 8 7h 8 70 e t a r e l p m a s0 e t a r e l p m a s 0 e t a r e l p m a s 0 e t a r e l p m a s0 e t a r e l p m a s5 1 0 r s5 1 0 r s 5 1 0 r s 5 1 0 r s5 1 0 r s4 1 0 r s4 1 0 r s 4 1 0 r s 4 1 0 r s4 1 0 r s3 1 0 r s3 1 0 r s 3 1 0 r s 3 1 0 r s3 1 0 r s2 1 0 r s2 1 0 r s 2 1 0 r s 2 1 0 r s2 1 0 r s1 1 0 r s1 1 0 r s 1 1 0 r s 1 1 0 r s1 1 0 r s0 1 0 r s0 1 0 r s 0 1 0 r s 0 1 0 r s0 1 0 r s9 0 r s9 0 r s 9 0 r s 9 0 r s9 0 r s8 0 r s8 0 r s 8 0 r s 8 0 r s8 0 r s7 0 r s7 0 r s 7 0 r s 7 0 r s7 0 r s6 0 r s6 0 r s 6 0 r s 6 0 r s6 0 r s5 0 r s5 0 r s 5 0 r s 5 0 r s5 0 r s4 0 r s4 0 r s 4 0 r s 4 0 r s4 0 r s3 0 r s2 0 r s2 0 r s 2 0 r s 2 0 r s2 0 r s1 0 r s1 0 r s 1 0 r s 1 0 r s1 0 r s0 0 r s0 0 r s 0 0 r s 0 0 r s0 0 r sh 0 8 b bh 0 8 b b h 0 8 b b h 0 8 b bh 0 8 b b note: 32h is an alias for 78h. the vra bit in register 2ah must be set for the alias to w ork; if a zero is written to vra then both sample rates are reset to 48k. sr0[15:0] w riting to this register allows the user to program the sampling frequency from 7 khz (1 b58h) to 48 khz (bb80h) in 1 hertz increments. programming a value greater than 48 khz or less than 7 khz may cause unpredictable resu lts.
AD1881A C20C rev. 0 sample rate 1 (index 7ah) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h a 7h a 7 h a 7 h a 7h a 71 e t a r e l p m a s1 e t a r e l p m a s 1 e t a r e l p m a s 1 e t a r e l p m a s1 e t a r e l p m a s5 1 1 r s5 1 1 r s 5 1 1 r s 5 1 1 r s5 1 1 r s4 1 1 r s4 1 1 r s 4 1 1 r s 4 1 1 r s4 1 1 r s3 1 1 r s3 1 1 r s 3 1 1 r s 3 1 1 r s3 1 1 r s2 1 1 r s2 1 1 r s 2 1 1 r s 2 1 1 r s2 1 1 r s1 1 1 r s1 1 1 r s 1 1 1 r s 1 1 1 r s1 1 1 r s0 1 1 r s0 1 1 r s 0 1 1 r s 0 1 1 r s0 1 1 r s9 1 r s9 1 r s 9 1 r s 9 1 r s9 1 r s8 1 r s8 1 r s 8 1 r s 8 1 r s8 1 r s7 1 r s7 1 r s 7 1 r s 7 1 r s7 1 r s6 1 r s6 1 r s 6 1 r s 6 1 r s6 1 r s5 1 r s5 1 r s 5 1 r s 5 1 r s5 1 r s4 1 r s4 1 r s 4 1 r s 4 1 r s4 1 r s3 1 r s3 1 r s 3 1 r s 3 1 r s3 1 r s2 1 r s2 1 r s 2 1 r s 2 1 r s2 1 r s1 1 r s1 1 r s 1 1 r s 1 1 r s1 1 r s0 1 r s0 1 r s 0 1 r s 0 1 r s0 1 r sh 0 8 b bh 0 8 b b h 0 8 b b h 0 8 b bh 0 8 b b note: 2ch is an alias for 7ah. the vra bit in register 2ah must be set for the alias to work; if a zero is written to vra, both sample rates are reset to 48k. sr1[15:0] writing to this register allows the user to program the sampling frequency from 7 khz (1b58h) to 48 khz (bb80h) in 1 hertz increments. programming a value greater than 48 khz or less than 7 khz may cause unpre dictable results. vendor id registers (index 7ch?eh) g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h c 7h c 7 h c 7 h c 7h c 71 d i r o d n e v1 d i r o d n e v 1 d i r o d n e v 1 d i r o d n e v1 d i r o d n e v7 f7 f 7 f 7 f7 f6 f6 f 6 f 6 f6 f5 f5 f 5 f 5 f5 f4 f4 f 4 f 4 f4 f3 f3 f 3 f 3 f3 f2 f2 f 2 f 2 f2 f1 f1 f 1 f 1 f1 f0 f0 f 0 f 0 f0 f7 s7 s 7 s 7 s7 s6 s6 s 6 s 6 s6 s5 s5 s 5 s 5 s5 s4 s4 s 4 s 4 s4 s3 s3 s 3 s 3 s3 s2 s2 s 2 s 2 s2 s1 s1 s 1 s 1 s1 s0 s0 s 0 s 0 s0 sh 4 4 1 4h 4 4 1 4 h 4 4 1 4 h 4 4 1 4h 4 4 1 4 s[7:0] this register is ascii encoded to ?. f[7:0] this register is ascii encoded to ?. g e rg e r g e r g e rg e r m u nm u n m u n m u nm u n e m a ne m a n e m a n e m a ne m a n5 1 d5 1 d 5 1 d 5 1 d5 1 d4 1 d4 1 d 4 1 d 4 1 d4 1 d3 1 d3 1 d 3 1 d 3 1 d3 1 d2 1 d2 1 d 2 1 d 2 1 d2 1 d1 1 d1 1 d 1 1 d 1 1 d1 1 d0 1 d0 1 d 0 1 d 0 1 d0 1 d9 d9 d 9 d 9 d9 d8 d8 d 8 d 8 d8 d7 d7 d 7 d 7 d7 d6 d6 d 6 d 6 d6 d5 d5 d 5 d 5 d5 d4 d4 d 4 d 4 d4 d3 d3 d 3 d 3 d3 d2 d2 d 2 d 2 d2 d1 d1 d 1 d 1 d1 d0 d0 d 0 d 0 d0 dt l u a f e dt l u a f e d t l u a f e d t l u a f e dt l u a f e d h e 7h e 7 h e 7 h e 7h e 72 d i r o d n e v2 d i r o d n e v 2 d i r o d n e v 2 d i r o d n e v2 d i r o d n e v7 t7 t 7 t 7 t7 t6 t6 t 6 t 6 t6 t5 t5 t 5 t 5 t5 t4 t4 t 4 t 4 t4 t3 t3 t 3 t 3 t3 t2 t2 t 2 t 2 t2 t1 t1 t 1 t 1 t1 t0 t0 t 0 t 0 t0 t7 v e r7 v e r 7 v e r 7 v e r7 v e r6 v e r6 v e r 6 v e r 6 v e r6 v e r5 v e r5 v e r 5 v e r 5 v e r5 v e r4 v e r4 v e r 4 v e r 4 v e r4 v e r3 v e r3 v e r 3 v e r 3 v e r3 v e r2 v e r2 v e r 2 v e r 2 v e r2 v e r1 v e r1 v e r 1 v e r 1 v e r1 v e r0 v e r0 v e r 0 v e r 0 v e r0 v e rh 8 4 3 5h 8 4 3 5 h 8 4 3 5 h 8 4 3 5h 8 4 3 5 t[7:0] this register is ascii encoded to ?. rev[7:0] revision register field. these bits are read-only and should be verified before accessing vendor defined features. AD1881A/ad1881 user visible differences pin 48 is now mode pin, no longer chain_clk. ad1881 chaining mode not supported. lsb of register 7eh is 48h instead of 40h.
AD1881A C21C rev. 0 applications circuits the AD1881A has been designed to require a minimum amount of external c ircuitry. the recommended applications circuits are shown in figure 9. reference designs for the AD1881A are available and may be obtained by contacting your local analog d evices sales representative or authorized distributor. reset sdata_out sdata_in sync bit_clk cs0 cs1 eapd mode digital controller 10 f 100nf +5av dd av dd2 av ss2 av dd1 av ss1 dv ss1 dv dd1 dv ss2 dv dd2 afilt1 afilt2 filt_l phone_in mono_out line_out_r line_out_l 47k 47k 47k 1 f 24.576mhz 22pf np0 22pf np0 10 f tant 100nf 47nf 2.25v dc 100nf 1 f 270pf np0 270pf np0 filt_r cx3d rx3d v refout v ref xtl_in xtl_out 600z analog ground digital ground AD1881A pc_beep line_in_r line_in_l mic1 mic2 cd_r cd_l cd_gnd video_l video_r aux_l aux_r 0.33 f 0.33 f 0.33 f 0.33 f 0.33 f 0.33 f 0.33 f 7 36 34 33 27 10k 47 48 1k 100nf 100nf 28 0.33 f 0.33 f 0.33 f 0.33 f 0.33 f 0.33 f 47pf 47 100nf 100nf 100nf +3.3dv dd 10 f 39 41 47k 1 f 47k 1 f lnlvl_out_l lnlvl_out_r 1 f 1 f eapd note: for optimal performance use a regulated analog power supply. figure 9. recommended one codec application circuit
AD1881A C22C rev. 0 cd-rom connections the cd-rom audio output level should be investigated; typical drives generate 2 v rms output and re quire a voltage divider for compatibility with the codec input (1 v rms range). the recommended circuit is basically a group of divide-by-two voltage divid ers as shown on figure 10. the cd_gnd_ref pin is used to cancel differential ground noise from the cd-rom. for optimum noise cancellation, this section of the divider should have approximately half the impedance of the right and left channel section dividers. header for cd rom audio (lggr) 1 2 3 4 voltage divider r1 4.7k r3 2.7k 4.7k r5 r2 4.7k r4 2.7k r6 4.7k c1 0.33 f 0.33 f 0.33 f c2 c3 to codec cd_l input to codec cd_gnd_ref input to codec cd_r input + + + figure 10. typical cd-rom audio connections line_in, aux and video input connections most of these audio sources also generate 2 v rms audio level and require a ? db input voltage divider to be compatible with the codec inputs. figure 11 shows the recommended application circuit. for applications requiring emc compliance, the emc compo- nents should be configured and selected to provide adequate rf immunity and emissions control. 1 2 3 4 r1 4.7k r2 4.7k c3 0.33 f 0.33 f c4 to codec right channel input + + 5 r3 4.7k r4 4.7k to codec left channel input l2 600z l1 600z c1 470pf c2 470pf emc components voltage divider ac-coupling line/aux/video input j1 figure 11. line_in, aux, and video input connections microphone connections the AD1881A contains an internal microphone preamp with 20 db gain, in most cases a direct microphone connection as shown in figure 12 is adequate. if the microphone level is too low, an external preamp can be added as shown in figure 13. in either cas e the microphone bias can be derived from the codec? internal reference (v refout ) using a 2.2 k ? resistor. for the preamp circuit, the v refout signal can also provide the mid-point bias for the amplifier. to meet the pc99 1.0a requirements, the mic signal s hould be placed on the microphone jack tip and the bias on the ring. this configuration supports electret microphones with three conductor plugs, as well as dynamic microphones with two conductor plugs (ring and sleeve shorted together). additional filtering may be required to limit the microphone response to the audio band of interest.
AD1881A C23C rev. 0 1 2 3 4 c3 0.22 f 2.2k r1 to codec mic1 or mic2 input 5 from codec v refout l1 600z l2 600z c1 470pf c2 470pf emc components mic input j1 ac-coupling )
*# 2
+ r2 10k r3 100k preamp ad8531 u1 1 2 3 4 c3 0.22 f 2.2k r1 to codec mic1 or mic2 input 5 from codec v refout l1 600z l2 600z c1 470pf c2 470pf emc components mic input j1 ac-coupling c3 0.22 f ac-coupling mic bias +5av dd figure 13. microphone with additional external preamp (20 db gain) line output connections the AD1881A codec provides stereo line_out signals at a standard 1 v rms level. these signals must be ac-coupled before they can be connected to an external load. after the ac-coupling, a minimal resist ive load is recommended to keep the capacitors properly biased and reduce click and pop when plugging stereo equipment into the output jack. the capacitor values should be selected to provide a desired frequency response, taking into account the nominal impedance of the external load. to meet the pc99 specification for pcs, testing must be performed with a 10 k ? load, therefore a 1 f value is recommended to achieve less than ? db roll-off at 20 hz. from codec line_out_r l2 600z l1 600z c1 470pf c2 470pf emc components stereo line_out jack j1 c1 1 f 1 f c2 + + ac-coupling r1 47k r2 47k from codec line_out_l note: if an output amp is used, the ac-coupling cap values will depend on the amp design. figure 14. recommended line_out connections using an external headphone/power amp the ssm2250 power amplifier is an ideal companion for the AD1881A. the amplifier can provide up to 250 mw output in stereo mode and up to 1.5 w into a mono speaker connected in a bridge-tied load (btl) configuration. the sm2250 has a mode control pin that can be used to switch between the stereo output mode and the mono btl speaker. figure 15 shows a typical pc configuration where the ssm2250 drives a set of stereo headphones or external speakers, as well as an internal mono speaker. one of the normalizing pins on the stereo jack senses the stereo plug insertion and automatically sw itches from driving the internal mono speaker to driving the external stereo load. to conserve power, the ssm2250 can be shut down by the eapd pin on the AD1881A, using proper power management software. this is particularly important for portable applications. in shutdown mode, the ssm2250 consumes only 60 a.
AD1881A C24C rev. 0 eapd/chain_in mono_out line_out_l lin_out_r AD1881A nc left in shutdown se/btl gnd right in nc nc left out/blt vdo btl+ bypass right out nc u2 ssm2250ru c4 0.33 f c7 0.33 f r4 49.9k r6 49.9k nc = no connect r2 49.9k u1 r7 49.9k c8 0.1 f c1 1 f r1 100k c2 100 f r3 1k fb 600z c3 470pf c5 100 f r5 1k fb 600z c6 470pf f1 f2 stereo hp/speaker output j1 stereo 3.5mm jack ls1 internal mono speaker 4 5av dd figure 15. using the ssm2250 amplifier for stereo and mono output grounding and layout to reduce noise and emissions, analog devices recommends a split ground plane as shown in figure 16. the purpose of splitting t he ground plane is to cr eate a low noise analog area that is somewhat isolated from the digital ground current noise generated by the system? logic. all the analog circuitry should be placed on the analog ground plane area. for reference purposes, and to return power supply currents, the analog and digital ground planes must be connected at some poi nt, ideally a small bridge under or near the codec should be provided. a 0 ? resistor or a ferrite bead should also be considered since these allow some flexibility in optimizing the layout to meet emc requirements. pin 1 isolation trench connect split ground planes at or near codec. analog ground plane digital ground plane AD1881A figure 16. recommended split ground plane analog power supply to minimize audio noise, the codec analog power supply (avdd) should be well decoupled and regulated. in pc systems it is rec- ommended that the analog supply be d erived from the 12 v pc power supply using a localized linear voltage regulator. preferably, the analog power supply should be connected to the codec? analog section using a ferrite bead.
AD1881A C25C rev. 0 c2 0.1 600z 12v l1 f 3 out c1 + lm78m05cp in gnd 5av dd c3 c4 10 u1 2 + r1 0 10 f 0.1 ff figure 17. recommended regulator circuit for analog power supply if a power plane layer is being used in the system design, it is recommended that the analog power plane for the codec also be split (mirroring the analog ground plane). in this case, the analog power supply ferrite bead should bridge the isolation trench, clo se to the codec location.
AD1881A C26C rev. 0 outline dimensions dimensions shown in inches and (mm). 48-lead thin plastic quad flatpack (lqfp) (st-48) 0.276 (7.0) bsc 1 12 13 25 24 36 37 48 top view (pins down) 0.276 (7.0) bsc 0.354 (9.00) bsc 0.011 (0.27) 0.006 (0.17) 0.020 (0.5) bsc 0.354 (9.00) bsc seating plane 0.063 (1.60) max 0 min 0 7 0.006 (0.15) 0.002 (0.05) 0.030 (0.75) 0.018 (0.45) 0.057 (1.45) 0.053 (1.35) 0.030 (0.75) 0.018 (0.45) 0.007 (0.18) 0.004 (0.09) c3747C8C4/00 (rev. 0) 00752 printed in u.s.a.

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